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87c196ca/87c196cb 20 mhz advanced 16-bit chmos microcontroller with integrated can 2.0 express advance information datasheet product features ?40c to +85c ambient high performance chmos 16-bit cpu up to 32 kbytes of on-chip eprom up to 1 kbyte of on-chip register ram up to 512 bytes of additional ram (code ram) register-register architecture 8 channel/10-bit a/d with sample/hold 37 prioritized interrupts up to seven 8-bit (56) i/o ports full duplex serial i/o port dedicated baud rate generator interprocessor communication slave port selectable bus timing modes for flexible interfacing oscillator fail detection circuitry high speed peripheral transaction server (pts) two dedicated 16-bit high-speed compare registers 10 high speed capture/compare (epa) full duplex synchronous serial i/o port (ssio) two flexible 16-bit timer counters quadrature counting inputs flexible 8-/16-bit external bus (programmable) programmable bus (hld/hlda) 1.4 s 16 x 16 multiply 2.4 s 32/16 divide 68-pin plcc package for 87c196ca 84-pin plcc package for 87c196cb 20 mhz operation order no: 273151-00 3 august 200 4 notice: this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
87c196ca/87c196cb - express ii advance information datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. d e s i gne r s mu s t not r e l y o n the a b s e n c e o r c h a r a c te r i s t i c s of a n y fe a t u r e s o r i n s t r u c t i on s ma r k ed " r e s e r v e d " o r " u ndef i ned. " in t e l r e s e r v e s the s e fo r f utu r e def i n i t i o n and s ha l l h a v e n o r e s p on s i b i l i t y w h a t s oe v e r fo r c onf l i c t s o r i n c o m p a t i b i l i t i e s a r i s i n g f r om f u tu r e c h ange s t o t h em. t h e p r odu c t m a y c onta i n de s i g n defe c t s o r e rr o r s k no w n a s e r r ata w h i c h ma y c a u s e the p r od u c t t o de v i a t e f r om p u b l i s h e d s p e c i f i c a t i on s . cu r r e n t c ha r a c te r i z ed e r r ata a r e a v a i l ab l e o n r e que s t. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. alertview, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct connect, ct media, dialogic, dm3, ethere xpress, etox, flashfile, i386, i486, i960, icomp, instantip, intel, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intel sx2, intel create & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel p lay, intel play logo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, landesk, lanrov er, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, trillium, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsi diaries in the united states and other countries.
advance information datasheet iii 87c196ca/87c196cb - express contents 1.0 introduction ................................................................................................................. 1 2.0 block diagram ............................................................................................................. 2 3.0 process information .............................................................................................. 3 4.0 pin descriptions ........................................................................................................... 6 5.0 electrical characteristics ......................................................................... 11 5.1 dc characteristics ..........................................................................................11 5.1.1 8xc196cb additional bus timing modes...................................................14 5.1.1.1 mode 3 .........................................................................................14 5.1.1.2 mode 0 .........................................................................................14 5.2 ac characteristics ..........................................................................................14 5.2.1 test conditions .............................................................................................14 5.2.2 87c196ca/87c196cb - express timings ...................................................17 5.2.3 87c196cb timings ......................................................................................18 5.2.4 8xc196cb timings ......................................................................................19 5.2.5 8xc196cb ac characteristics - slave port .................................................20 5.2.6 explanation of ac symbols .........................................................................24 5.3 eprom specifications................................................................................................25 5.3.1 ac eprom programming characteristics...................................................25 5.3.2 eprom programming waveforms ..............................................................26 5.4 ac characteristics - serial port - shift register mode ..................................28 5.4.1 a/d characteristics .......................................................................................28 5.4.1.1 a/d converter specification ..........................................................29 5.4.2 87c196ca design considerations ...............................................................32 5.4.3 87c196ca errata ...................................................................................33 5.4.4 87c196ca design considerations .................................................33 6.0 datasheet revision history .......................................................................... 34
87c196ca/87c196cb - express iv advance information datasheet figures 1 8xc196cb block diagram.......................................................................................... 2 2 the 87c196ca/87c196cb - express family nomenclature...................................... 3 3 84-pin plcc xx 87c196cb diagram ............................................................ .............. 4 4 68-pin plcc xx 87c196ca diagram ............................................................. ............. 5 5 chip configuration registers ..................................................................................... 10 6 87c196ca i cc vs frequency ..................................................................................... 13 7 87c196cb i cc vs frequency ..................................................................................... 13 8 87c196ca/87c196cb - express system bus timing .............................................. 17 9 87c196ca/87c196cb - express ready timings (one wait state) ......................... 18 10 87c196cb buswidth timings.................................................................................... 18 11 87c196cb hold#/holda# timings..................................................................... 19 12 slave port waveform - (slpl = 0) ............................................................................ 20 13 slave port waveform - (slpl = 1) ............................................................................ 21 14 synchronous serial port ............................................................................................. 23 15 external clock drive waveforms .............................................................................. 24 16 input test conditions ................................................................................................. 24 17 output test conditions............................................................................................... 24 18 slave programming mode data program mode with single program pulse............. 26 19 slave programming mode in word dump or data verify mode with auto increment ................................................................................................... 27 20 slave programming mode timing in data program mode with repeated program pulse and auto increment .................................................... 27 21 waveform - serial port - shift register mode 0 ........................................................ 28 22 ad_time 1fafh:byte............................................................................................. 29 tables 1 device overview .......................................................................................................... 1 1 thermal characteristics ................................................................................................ 3 2 pin descriptions............................................................................................................ 6 3 87c196cb memory map ............................................................................................. 8 4 87c196ca memory map ............................................................................................. 9 5 dc characteristics (under listed operating conditions).......................................... 11 6 ac characteristics the 87c196ca/87c196cb - express meets ............................... 14 7 ac characteristics system must meet to work with 87c196ca/87c196cb - express....................................................................... 16 8 8xc196cb hold#/holda# timings (over specified operation conditions) ...................................................................... 19 9 slave port timing - (slpl = 0, 1, 2, 3) ..................................................................... 20 10 slave port timing - (slpl = 1, 2, 3) ......................................................................... 21 11 normal master/slave operation ................................................................................. 22 12 handshake operation ................................................................................................. 22 13 external clock drive .................................................................................................. 23 14 explanation of ac symbols ....................................................................................... 25 15 ac eprom programming characteristics ................................................................ 25 16 dc eprom programming characteristics ................................................................ 26 17 serial port timing - shift register mode................................................................... 28 18 10-bit mode a/d operating conditions .................................................................... 29 19 10-bit mode a/d characteristics (using above operating conditions)................... 30 20 8-bit mode a/d operating conditions ...................................................................... 30 21 8-bit mode a/d characteristics (using above operating conditions)..................... 31
advance information datasheet 1 87c196ca/87c196cb - express 1.0 introduction the 87c196ca/87c196cb - express are members of the mcs ? 96 microcontroller family. these devices are based upon the mcs 96 kx/jx microcontroller product families with enhancements ideal for automotive and industrial applications. the ca/cb are the first devices in the kx family to support networking through the integration of the can 2.0 (controller area network) peripheral on-chip. the 87c196cb offers the highest memory density of the mcs 96 microcontroller family, with 56k of on-chip eprom, 1.5k of on-chip register ram, and 512 bytes of additional ram (code ram). in addition, the 87c196cb provides up to 16 mbyte of linear address space. the 87c196ca is a sub-set of the cb, offering 32k of on-chip eprom, up to 1.0 k of on-chip register. table 1. device overview device pins/pack age eprom reg ram code ram i/o epa sio ssio can a/d addr space 87c196cb 84-pin plcc 56k 1.5k 512b 56 10 y y y 8 1 mbyte 87c196ca 68-pin plcc 32k 1.0k 256b 38 6 y y y 6 64 kbyte
87c196ca/87c196cb - express 2 advance information datasheet 2.0 block diagram the mcs 96 microcontroller family members are all high-performance microcontrollers with a 16-bit cpu. the 87c196cb is composed of the high-speed (20 mhz) macrocore with up to 16 mbyte linear address space, 56 kbytes of program eprom, up to 1.5 kbytes of register ram, and up to 512 bytes of code ram (16-bit addressing modes) with the ability to execute from this ram space. it supports the high-speed, serial communications protocol can 2.0, with 15 message objects of 8 bytes data length, an 8-channel, 10-bit / 3 lsb analog to digital converter with programmable s/h times, and conversion times k 20 ms at 20 mhz. it has an asynchronous/synchronous serial i/o port (sio) with a dedicated 16-bit baud rate generator, an additional synchronous serial i/o port (ssio) with full duplex master/slave transceivers, a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities. there are ten modularized, multiplexed, high-speed i/o for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs, and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (pts) implementing several channel modes, including single/burst block transfers from any memory location to any memory location, a pwm and pwm toggle mode to be used in conjunction with the epa, and an a/d scan mode. note: this is an advance information data sheet. the ac and dc parameters contained within this data sheet may change after full express temperature characterization of the device has been performed. contact your local sales office before finalizing the timing and dc characteristics of a design to verify you have the latest information. figure 1. 8xc196cb block diagram a4546-01 a/d converter sync serial port and baud gen watchdog timer event processor array alu 16 cpu microcode engine interrupt controller 512 bytes internal ram 56k on-chip eprom (optional) peripheral transaction server memory controller 1.5k byte register file s/h mux port 0 serial port baud rate gen port 6 port 1 port 2 can 2.0 timer 1 timer 2 queue port 6 ssio a/d port 0 port 1 epa port 2 / hold control rxcan txcan port 5 control signals port 3 ad0-7 port 4 ad8-15 eport a16-23 v ref angnd 16 8
adva n c e i n f o rm a t i o n dat a s h e e t 3 8 7 c 196 ca / 8 7 c 196 c b - ex p r e s s 3 . 0 p r o c e ss in f o r m a t i o n t h e s e d e v i c e s a r e m a nu f a c t u r e d o n p 6 2 9 . 5 , a chmo s i i i - e pr o c e s s . ad d i t i o n a l p r o c e s s a n d r e l i a b i l i t y i n f o r m a t i on i s a v a i l a b l e in t h e i n te l ? qu a l it y syste m handb o o k : http://developer.intel.com/design/quality/quality.ht m al l t h e r m a l i m p e d a n c e d a t a i s a p pro x i m a t e f o r s t a t i c a i r c o n d i t ion s a t 1 w o f p o w e r d i s s i p a t i on . v a l u e s c h a ng e d e p e ndi n g o n o p e r a t i on c on d it i on s a n d a ppl i c a t i on s . s e e t h e in t e l p a c k a g ing han d boo k (o r d e r nu m b e r 2 40800 ) f o r a d e s c r i pt i on of in t e l ' s t h e r m a l i m p e d a n c e t e s t m e th o dol o g y . f i g u re 2 . t h e 87c19 6 c a / 87c1 9 6cb - e x p r e s s f a m i l y n o m e n c l a t u r e t a b l e 1 . t h e r m a l c h a r a c t e r i s t i c s d e v i ce a n d p a c k a g e ja jc x x 8 7 c 1 96 cb ( 8 4 - l ead p l cc p ac k age ) 3 5 c / w 11 c / w x x 8 7 c 1 96 c a ( 6 8 - l ead p l cc p ac k age ) 3 6 . 5 c / w 1 0 c / w n o te s : 1 . j a = t h e r m a l r e s i s t a n ce b e t w e e n j u n c t i o n an d t h e s u rr o u n d i n g en v i r o nme n t ( a m b i e n t ) mea s u r emen t s a r e t a k e n 1 f t . a w ay fr o m ca s e i n a i r f l o w en v i r o nme n t . j v = t h e r ma l r e s i s t a n ce be t w ee n j u n c ti on an d p ac k age f ace ( ca s e ) . 2 . a ll v a l u e s o f j a a nd j c m a y f l uc t u a t e d e pe n d i n g o n t h e e nv i r o n m en t ( w it h o r w i t h ou t a i r f l o w , a n d ho w m u c h a i r f l o w ) a n d d e v i ce p o w e r d i ss i p a t i o n a t t e m p e r a t u r e o f op e r a t i o n . t y p i c a l v a r i a t i o n s a r e 2 c / w . 3 . v a l u e s li s t e d a r e a t a ma x i mum po w e r d i ss i p a t i o n o f 1 w . a4582-01 x x 8 7 c c a / b 1 9 6 7 = eprom, otp 0 = cpu product designation product family chmos technology program memory options: x = plcc (plastic leaded chip carrier) package type options: x = -40 ? c to + 85 ? c ambient with intel standard burn-in temperature and burn-in options: 4 . to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
87c196ca/87c196cb - express 4 advance information datasheet figure 3. 84-pin plcc xx 87c196cb diagram a4581-01 pllen p6.3 / t1dir p6.2 / t1clk p6.1 / epa9 p6.0 / epa8 p1.0 / epa0 p1.1 / epa1 p1.2 / epa2 p1.3 / epa3 p1.4 / epa4 p1.5 / epa5 p1.6 / epa6 p1.7 / epa7 v ss1 v cc v ref agnd p0.7 / ach7 p0.6 / ach6 p0.5 / ach5 p0.4 / ach4 p5.2 / wr# p5.5 /bhe# p5.3 / rd# v pp p5.0 / ale p5.1 / inst p5.6 / ready p5.4 / slpint ep3.3 / a19 v cc v ss1 v ss rxcan txcan xtal1 xtal2 p6.7 / sd1 p6.6 / sc1 p6.5 / sd0 p6.4 / sc0 v cc ps.7 / busw ep3.1 / a17 ep3.0 / a16 p4.7 / ad15 p4.6 / ad14 p4.5 / ad13 p4.4 / ad12 p4.3 / ad11 p4.2 / ad10 p4.1 / ad9 p4.0 / ad8 v ss1 v cc p3.7 / ad7 p3.6 / ad6 p3.5 / ad5 p3.4 / ad4 p3.3 / ad3 p3.2 / ad2 p3.1 / ad1 ep3.2 / a18 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 xx87c196cb 84-lead plcc view of component as mounted on pc board 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p3.0 / ad0 reset nmi ea# v ss1 v cc v ss p2.0 / txd p2.1 / rxd p2.2 / extint p2.3 / intb# p2.4 / intintout# p2.5 / hld# p2.6 / hlda# p2.7 / clkout v cc v ss1 p0.0 / ach0 p0.1 / ach1 p0.2 / ach2 p0.3 / ach3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
advance information datasheet 5 87c196ca/87c196cb - express figure 4. 68-pin plcc xx 87c196ca diagram a4583-01 nc nc v cc epa9 / p6.1 epa8 / p6.0 epa0 / p1.0 / t2clk epa1 / p1.1 epa2 / p1.2 / t2dir epa3 / p1.3 nc v ref angnd ach7 / p0.7 ach6 / p0.6 ach5 / p0.5 ach4 / p0.4 nc wr# / p5.2 wrh# / p5.5 rd# / p5.3 v pp v ss ale / p5.0 ready / p5.6 p5.4 v ss1 xtal1 xtal2 rxcan txcan sd1 / p6.7 sc1 / p6.6 sd0 / p6.5 sc0 / p6.4 nc ad15 / p4.7 ad14 / p4.6 ad13 / p4.5 ad12 / p4.4 ad11 / p4.3 ad10 / p4.2 ad9 / p4.1 ad8 / p4.0 ad7 / p3.7 ad6 / p3.6 ad5 / p3.5 ad4 / p3.4 ad3 / p3.3 ad2 / p3.2 nc nc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 xx87c196ca 68 ? ld plcc view of component as mounted on pc board 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p3.1 / ad1 p3.0 / ad0 reset# nmi ea# v ss1 v cc v ss txd / p2.0 rxd / p2.1 extint / p2.2 p2.4 p2.6 clkout / p2.7 ach2 / p0.2 ach3 / p0.3 nc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
87c196ca/87c196cb - express 6 advance information datasheet 4.0 pin descriptions table 2. pin descriptions (sheet 1 of 2) name description v cc main supply voltage (+5 v). v ss , v ss1 digital circuit ground (0 v). there are seven v ss pins cb (4 on ca), all of which must be connected to a single ground plane. v ref reference for the a/d converter (+5 v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. v pp programming voltage for the eprom parts. it should be +12.5 v for programming. it is also the timing pin for the return from powerdown circuit. connect this pin with a 1 f capacitor to v ss and a 1 m ? resistor to v cc . if this function is not used, v pp may be tied to v cc . angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . xtal1 input of the oscillator inverter and the internal clock generator. xtal2 output of the oscillator inverter. reset# reset input to the chip. input low for at least 16 state times resets the chip. the subsequent low-to-high transition resynchronizes clkout and commences a 10-state time sequence in which the psw is cleared, bytes are read from 2018h, 201ah and 201ch (if enabled) loading the ccbs, and a jump to location 2080h is executed. input high for normal operation. reset# has an internal pullup. nmi a positive transition causes a non-maskable interrupt vector through memory location 203eh. if not used, this pin should be tied to v ss . may be used by intel evaluation boards. ea# input for memory select (external access). ea# equal to a high causes memory accesses to locations 0ff2000h through 0fffffh to be directed to on-chip eprom/rom. ea# equal to a low causes accesses to these locations to be directed to off- chip memory. ea# = +12.5 v causes execution to begin in the programming mode. ea# latched at reset. pllen (196cb only) selects between pll mode or pll bypass mode. this pin must be either tied high or low. pllen pin = 0, bypass pll mode. pllen pin = 1, places a 4x pll at the input of the crystal oscillator. allows for a low frequency crystal to drive the device (i.e., 5 mhz = 20 mhz operation). p6.4-6.7/ssio dual-function i/o ports that have a system function as synchronous serial i/o. two pins are clocks and two pins are data, providing full duplex capability. also, lsio when not used as ssio. p6.3/t1dir (cb only) dual-function i/o pin. primary function is that of a bidirectional i/o pin, however, it may also be used as a timer1 direction input. the timer1 increments when this pin is high and decrements when this pin is low. p6.2/t1clk (cb only) dual-function i/o pin. primary function is that of a bidirectional i/o pin, however may also be used as a timer1 clock input. the timer1 increments or decrements on both positive and negative edges of this pin. p6.0-6.1/epa8-9 dual-function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. p5.7/buswidth (cb only) input for bus width selection. if ccr bit 1 is a one and ccr1 bit 2 is a one, this pin dynamically controls the buswidth of the bus cycle in progress. if buswidth is low, an 8-bit cycle occurs, if buswidth is high, a 16-bit cycle occurs. if ccr bit 1 is ?0? and ccr1 bit 2 is ?1?, all bus cycles are 8-bit, if ccr bit 1 is ?1? and ccr1 bit 2 is ?0?, all bus cycles are 16-bit. ccr bit 1 = ?0? and ccr1 bit 2 = ?0? is illegal. also an lsio pin when not used as buswidth. p5.6/ready ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of cl kout, the memory controller goes into a wait state mode un til the next positive transition in clkout occurs with ready high. when external memory is not used, ready has no effect. the max number of wait states inserted into the bus cycle is controlled by the ccr/ccr1. also an lsio if ready is not selected.
advance information datasheet 7 87c196ca/87c196cb - express p5.5/bhe#/wrh# byte high enable or write high output, as selected by the ccr. bhe# = 0 selects the bank of memory that is connected to the high byte of the data bus. a0 = 0 selects the bank of memory that is connected to the low byte. thus accesses to a 16-bit wide memory can be to the low byte only (a0 = 0, bhe# = 1), to the high byte only (a0 = 1, bhe# = 0) or both bytes (a0 = 0, bhe# = 0). if the wrh# function is selected, the pin goes low if the bus cycle is writing to an odd memory location. bhe#/wrh# is only valid during 16-bit external. also an lsio pin when not bhe/wrh#. p5.4/slpint dual-function i/o pin. as a bidirectional port pin or as a system function. the system function is a slave port interrupt output pin (on ca, bidirectional port pin only). p5.3/rd# read signal output to external memory. rd# is active only during external memory reads or lsio when not used as rd#. p5.2/wr#/wrl# write and write low output to external memory, as selected by the ccr, wr# goes low for every external write, while wrl# goes low only for external writes where an even byte is being written. wr#/wrl# is active during external memory writes. also an lsio pin when not used as wr#/wrl#. p5.1/inst (cb only) output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is active only during external memory fetches, during internal eprom fetches inst is held low. also lsio when not inst. p5.0/ale/adv# address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv#, it goes inactive (high) at the end of the bus cycle. adv# can be used as a chip select for external memory. ale/adv# is active only during external memory accesses. also lsio when not used as ale. port3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. p2.7/clkout output of the internal clock generator. the frequency is the oscillator frequency. cl kout has a 50% duty cycle. also lsio pin when not used as clkout. p2.6/hlda# bus hold acknowledge. active-low output indicates that the bus controller has relinquished control of the bus. occurs in response to an external device asserting the hld# signal. also lsio when not used as hlda#. p2.5/hldy (cb only) bus hold. active-low signal indicates that an external device is requesting control of the bus. also lsio when not used as hld#. p2.4/intout# interrupt output. this active-low output indicates that a pending interrupt requires use of the external bus. also lsio when not used as intout#. p2.3/breq# (cb only) bus request. this active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. also lsio when not used as breq#. p2.2/extint a positive transition on this pin causes a maskable interrupt vector through memory location 203ch. also lsio when not used as extint. p2.1/rxd receive data input pin for the serial i/o port. also lsio if not used as rxd. p2.0/txd transmit data output pin for the serial i/o port. also lsio if not used as txd. port 1/epa0?7 dual-function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. epa0 and epa2 have another function of t2clk and t2dir of the timer2 timer/counter. port 0/ach0?7 8-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to eprom parts to select the programming mode. eport (cb only) 8-bit bidirectional standard and i/o port. these bits are shared with the extended address bus, a16?a19 for cb plcc. pin function is selected on a per pin basis. txcan push-pull output to the can bus line. rxcan high impedance input-only from the can bus line. table 2. pin descriptions (sheet 2 of 2) name description
87c196ca/87c196cb - express 8 advance information datasheet table 3. 87c196cb memory map address description notes ffffffh ff2080h program memory - internal eprom or external memory (determined by ea# pin) ff207fh ff2000h special purpose memory - internal eprom or external memory (determined by ea# pin) ff1fffh ff0600h external memory ff05ffh ff0400h internal ram (identically mapped into 00400h005ffh) ff03ffh ff0100h external memory ff00ffh ff0000h reserved for ice feffffh 0f0000h overlaid memory (external) (5) 0effffh 010000h 900 kbytes external memory 00ffffh 002080h external memory or remapped otprom (program memory) (1) 00207fh 002000h external memory or remapped otprom (special purpose memory) (1,3) 001fffh 001fe0h memory mapped special function registers (sfr's) 001fdfh 001f00h internal peripheral special function registers (sfr's) (5) 001effh 001e00h internal can peripheral memory (5) 001dffh 001c00h internal register ram 001bffh 000600h external memory 0005ffh 000400h internal ram (code ram) (address with indirect or indexed modes) 0003ffh 000100h register ram upper register file (address with indirect or indexed modes or through windows.) (2) 0000ffh 000018h register ram lower register file. (address with direct, indirect, or indexed modes.) (2) 000017h 000000h cpu sfr's (4) notes: 1. these areas are mapped internal eprom if the remap bit (ccb2.2) is set and ea# = 5 v. otherwise they are external memory. 2. code executed in locations 0000h to 003ffh is forced external. 3. reserved memory locations must contain 0ffh unless noted. 4. reserved sfr bit locations must be written with 0. 5. refer to 8xc196cb user's guide for sfr, can and paging descriptions.
advance information datasheet 9 87c196ca/87c196cb - express table 4. 87c196ca memory map address description notes 00ffffh 00a000h external memory 009fffh 002080h internal eprom (32 kbytes) 00207fh 002000h (determined by ea# pin) reserved memory (internal eprom or external memory) 001fffh 001fe0h memory mapped special function registers (sfr's) 001fdfh 001f00h internal special function registers (sfr's) (1) 001effh 001e00h internal can peripheral memory 001dffh 000500h external memory 0004ffh 000400h (address with indirect or indexed modes) internal ram (code ram) 0003ffh 000100h internal register ram ? upper register file (address with indirect or indexed modes or through windows) (2) 0000ffh 000018h internal register ram ? lower register file (address with direct, indirect, or indexed modes. (2) 000017h 000000h cpu special function registers (sfr's) (2,3) notes: 1. refer to 8xc196kx family user's guide for sfr description. 2. code executed in locations 0000h to 003ffh is forced external. 3. reserved sfr bit locations must be written with 0.
87c196ca/87c196cb - express 10 advance information datasheet figure 5. chip configuration registers ccb (2018h: byte) 0 1 2 3 4 5 6 7 pd bw0 wr ale irc0 irc1 loc0 loc1 = = = = = = = = ?1? enables powerdown see table ?1? = wr#/bhe - ?0? = wrl#/wrh# ?1? = ale - ?0? = adv } see table } see table ccb1 (201ah: byte) 0 1 2 3 4 5 6 7 ccr2 irc2 bw1 wde 1 0 memsel0 memsel1 = = = = = = = = ?1? fetch ccb2 (?0? for ca) see table see table ?0? = always enabled reserved must be ?1? reserved must be ?1? see table see table loc1 loc0 function irc2 irc1 irc0 max wait states 0 0 1 1 0 1 0 1 read and write protected write protected only read protected only no protection 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 zero wait states 1 wait state 2 wait states 3 wait states infinite msel1 msel0 ?cb? bus timing mode bw1 bw0 bus width 0 0 1 1 0 1 0 1 mode 0 (1-wait kr) mode 1 mode 2 mode 3 (kr) 0 0 1 1 0 1 0 1 illegal 16-bit only 8-bit only bw pin controlled mode 0 (1-wait kr): designed to be similar to the 87c196kr bus timing with 1 automatic wait state. see ac timings section for actual timings data. mode 3 (kr): designed to be similar to the 87c196kr bus timing. see ac timings section for actual timings data. ccb2 (201ch: byte) (cb only) 0 1 2 3 4 5 6 7 0 mode16 remap 1 1 1 1 1 = = = = = = = = reserved must be ?0? select 16-bit or 24-bit mode ?0??select eprom/coderam in segment 0ffh only ?1??select both segment 0ffh and segment 00h reserved must be ?1? reserved must be ?1? reserved must be ?1? reserved must be ?1? reserved must be ?1? }
advance information datasheet 11 87c196ca/87c196cb - express 5.0 electrical characteristics 5.1 dc characteristics absolute maximum ratings* storage temperature ?60c to +150c voltage from v pp or ea# to v ss or angnd............................. ....... ?0.5 v to +13.0 v voltage from any other pin to v ss or angnd............................. ....... ?0.5 v to +7.0 v this includes v pp on rom and cpu devices. power dissipation ....................................... 0.5 w operating conditions t a (ambient temperature under bias) ...........?40c to +85c v cc (digital supply voltage) 4.5 v to 5.5 v v ref (analog supply voltage) 4.5 v to 5.5 v f osc (oscillator frequency)........................... 4 mhz to 20 mhz note: angnd and v ss should be nominally at the same potential. notice: this is a production data sheet. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 5. dc characteristics (under listed operating conditions) (sheet 1 of 2) symbol parameter min typ max units te st conditions i cc v cc supply current (?40c to +85c ambient) ca cb 90 100 ma xtal1 = 20 mhz v cc = v pp = v ref = 5.5 v (while device in reset) i ref a/d reference supply current 5ma i idle idle mode current ca cb 40 35 ma xtal1 = 20 mhz v cc = v pp = v ref = 5.5 v i pd powerdown mode current 50 tbd a v cc = v pp = v ref = 5.5 v (notes 6,9) v il input low voltage (all pins) ?0.5 0.3 v cc vfor port0 (note 8) v ih input high voltage 0.7 v cc v cc + 0.5 v for port0 (note 8) notes: 1. all bd (bidirectional) pins except inst and clkout. inst and clkout are excluded due to not being weakly pulled high in reset. bd pins include port1, port2, port3, port4, port5 and port6 except splint (p5.4) and hlda (p2.6). 2. standard input pins include xtal1, ea#, reset and port 1/2/5/6 when setup as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. maximum i ol /i oh currents per pin are characterized and published at a later date. 6. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5 v. 7. violating these specifications in reset may cause the device to enter test mode (p5.4 and p2.6). 8. when p0 is used as analog inputs, refer to a/d specifications for this characteristic. 9. for temperatures < 100c typical is 10 a.
87c196ca/87c196cb - express 12 advance information datasheet v ol output low voltage (outputs configured as complementary) 0.3 0.45 1.5 v i ol = 200 a (note 3,5) i ol = 3.2 ma i ol = 7 ma v oh output high voltage (output configured as complementary) v cc ? 0.3 v cc ? 0.7 v cc ? 1.5 v i oh = ?200 a (note 3,5) i oh = ?3.2 ma i oh = ?7 ma i li input leakage current (standard inputs) 10 a v ss < v in < v cc i li1 input leakage current (port 0) ca 1.5 cb 1 a v ss < v in < v ref v oh1 splint (p5.4) and hlda (p2.6) output high voltage in reset 2vi oh = 0.8 ma (note 7) v oh2 output high voltage in reset v cc ? 1 v i oh = ?15 a (note 1) c s pin capacitance (any pin to v ss ) 10 pf f test = 1 mhz (note 6) r rst reset pull-up resistor (cb) 65 k 180 k ? for cb r rst reset pull-up resistor (ca) 6 k 65 k ? for ca r wpu weak pull-up resistance (approximate) 9150 k ? (note 6) table 5. dc characteristics (under listed operating conditions) (sheet 2 of 2) symbol parameter min typ max units te st conditions notes: 1. all bd (bidirectional) pins except inst and clkout. inst and clkout are excluded due to not being weakly pulled high in reset. bd pins include port1, port2, port3, port4, port5 and port6 except splint (p5.4) and hlda (p2.6). 2. standard input pins include xtal1, ea#, reset and port 1/2/5/6 when setup as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. maximum i ol /i oh currents per pin are characterized and published at a later date. 6. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref = v cc = 5 v. 7. violating these specifications in reset may cause the device to enter test mode (p5.4 and p2.6). 8. when p0 is used as analog inputs, refer to a/d specifications for this characteristic. 9. for temperatures < 100c typical is 10 a.
advance information datasheet 13 87c196ca/87c196cb - express figure 6. 87c196ca i cc vs frequency figure 7. 87c196cb i cc vs frequency a5862-01 90 80 70 60 50 40 30 20 10 0 2 8 14 20 active i cc max = 90 ma active i cc = 75 ma idle max = 40 ma idle i cc = 32 ma i cc = [ma] a5863-01 active i cc max = 100 ma active i cc = 83 ma idle max = 35 ma idle i cc = 28 ma 100 90 80 70 60 50 40 30 20 10 0 2 8 14 20 i cc = [ma]
87c196ca/87c196cb - express 14 advance information datasheet 5.1.1 8xc196cb additional bus timing modes the 8xc196cb device has two bus timing modes for external memory interfacing. 5.1.1.1 mode 3 mode 3 is the standard timing mode. use this mode for systems that emulate the 8xc196kr bus timings. 5.1.1.2 mode 0 mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus cycles. 5.2 ac characteristics 5.2.1 test conditions capacitive load on all pins = 100 pf rise and fall times = 10 ns table 6. ac characteristics the 87c196ca/87c196cb - express meets (sheet 1 of 2) symbol parameter min max units f xtal frequency on xtal1 420mhz (1) t osc xtal1 period (1/f xtal ) 50 250 ns t xhch xtal1 high to clkout high or low + 20 110 ns t ofd clock failure to reset pulled low 440 s (6) t clcl clkout period 2t osc ns t chcl clkout high period t osc ?10 t osc +15 ns t cllh clkout low to ale/adv high ?15 + 10 ns t llch ale/adv# lowe to clkout high ?20 + 15 ns t lhlh ale/adv# cycle time 4t osc ns (5) t lhll ale/adv# high time t osc ?10 t osc +10 ns t av l l address valid to ale low t osc ?15 ns t llax address hold after ale/adv# low t osc ?40 ns t llrl ale/adv# low to rd# low t osc ?30 ns notes: 1. testing performed at 4 mhz, however, the device is static by design and typically operates below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2t osc x n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. programming the cde bit enables oscillator fail detection.
advance information datasheet 15 87c196ca/87c196cb - express t rlcl rd low to clkout low ca cb + 4 ?8 + 30 + 20 ns t rlrh rd# low period t osc ?10 ns (5) t rhlh rd# high to ale/adv# high t osc t osc +25 ns (3) t rlaz rd# low to address float 5 ns t llwl ale/adv# low to wr# low t osc ?10 ns t clwl clkout low to wr# low ?5 + 25 ns t qvwh data valid before wr# high t osc ?23 ns t chwh clkout high to wr# high ?10 + 15 ns t wlwh wr# low period ca cb t osc ?30 t osc ?20 ns (5) t whqx data hold after wr# high t osc ?25 ns t whlh wr# high to ale/adv# high t osc ?10 t osc +15 ns (3) t whbx bhe#, inst hold after wr# high t osc ?10 ns t whax ad8-15 hold after wr# high t osc ?30 ns (4) t rhbx bhe#, inst hold after rd# high t osc ?10 ns t rhax ad8-15 hold after rd# high t osc ?30 ns (4) table 6. ac characteristics the 87c196ca/87c196cb - express meets (sheet 2 of 2) symbol parameter min max units notes: 1. testing performed at 4 mhz, however, the device is static by design and typically operates below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2t osc x n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. programming the cde bit enables oscillator fail detection.
87c196ca/87c196cb - express 16 advance information datasheet table 7. ac characteristics system must meet to work with 87c196ca/87c196cb - express symbol parameter min max units t av y v address valid to ready setup 20 ns (3) t llyv ale low to ready setup 250 ns (3) t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0t osc ?30 ns (1) t av g v address valid to buswidth setup t osc ?75 ns (2,3) t llgv ale low to buswidth setup t osc ?60 ns (2,3) t clgx buswidth hold after clkout low 0 ns t av d v address valid to input data valid 3t osc ?55 ns (2) t rldv rd# active to input data value ca cb t osc ?22 t osc ?30 ns (2) t cldv clkout low to input data valid 3t osc ?50 ns t rhdz end of rd# to input data valid ns t rhdx data hold after rd# high 0 ns notes: 1. testing performed at 4 mhz, however, the device is static by design and typically operates below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2t osc x n = number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. programming the cde bit enables oscillator fail detection.
advance information datasheet 17 87c196ca/87c196cb - express 5.2.2 87c196ca/87c196cb - express timings figure 8. 87c196ca/87c196cb - express system bus timing a5872-01 xtal1 clkout ale / adv# rd# wr# t osc t xhch t clcl t cllh t llch t lhlh t lhll t llrl t rldv t rlaz address out a0 ? a15 address out data out data in t wlwh bus read bus write bhe, inst valid address out ad8?ad15 valid 8-bit bus mode if mode 0 operation is selected, add 2 t osc to this time. bhe#, inst ad8?ad15 t avll t avdv t llwl t rlrh t llax t rhlh t rhdx t rhdz t qvwh t whqx t whax or t rhax t whbx or t rhbx
87c196ca/87c196cb - express 18 advance information datasheet 5.2.3 87c196cb timings figure 9. 87c196ca/87c196cb - express ready timings (one wait state) figure 10. 87c196cb buswidth timings a5837-01 clkout ale ready rd# bus read address out wr# bus write t llch t cllh t clcl t xhch xtal1 t osc t llyv t avyv t clyx (max) t clyx (min) t rlrh + 2 t osc t rhdx t avdv + 2 t osc data in address out t wlwh + 2 t osc t qvwh + 2 t osc data out if mode 0 selected (cb only), one wait state is always added. if additional wait states are required, add 2 t osc to these specifications. a5861-01 clkout ale bus width bus write xtal1 t osc t llgv t clgx t avgv valid valid address out address out data out if mode 0 selected (cb only), add 2 t osc to these specifications.
advance information datasheet 19 87c196ca/87c196cb - express 5.2.4 8xc196cb timings table 8. 8xc196cb hold#/holda# timings (over specified operation conditions) symbol parameter min max units t hvch hold setup time + 65 ns (1) t clhal clkout low to hlda low ?15 + 15 ns t clbrl clkout low to breq low ?15 + 15 ns t azhal hlda low to address float + 25 ns t bzhal hlda low to bhe#, inst, rd#, wr# weakly driven + 25 ns t clhah clkout low to hlda high ?15 + 15 ns t clbrh clkout low to breq high ?25 + 25 ns t hahax hlda high to address no longer float ?15 ns t hahbv hlda high to bhe#, inst, rd#, wr# valid ?10 + 15 ns note: 1. to guarantee recognition at next clock. figure 11. 87c196cb hold#/holda# timings a5848-01 clkout hold# holda# breq# bus bhe#, inst, rd#, wr# ale t chlh t clhah t clbrh t hahax t hahax t halbz t halaz t clbrl t clhal t hvch t hvch t osc hold latency
87c196ca/87c196cb - express 20 advance information datasheet 5.2.5 8xc196cb ac characteristics - slave port figure 12. slave port waveform - (slpl = 0) table 9. slave port timing - (slpl = 0, 1, 2, 3) symbol parameter min max units t savwl address valid to wr# low 50 ns t srhav rd# high to address valid 60 ns t srlrh rd# low period t osc ns t swlwh wr# low period t osc ns t srldv rd# low to output data valid 60 ns t sdvwh input data setup to wr# high 20 ns t swhqx wr# high to data invalid 30 ns t srhdz rd# high to data float 15 ns note: 1. test conditions: f osc = 20 mhz t osc = 50 ns rise/fall time = 10 ns capacitive pin load = 100 pf 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advance information and are subject to change. a5847-01 cs ale / a1 rd p3 wr t swlwh t srldv t srhav t savwl t srlrh t sdvwh t swhqx t srhdz
advance information datasheet 21 87c196ca/87c196cb - express figure 13. slave port waveform - (slpl = 1) table 10. slave port timing - (slpl = 1, 2, 3) symbol parameter min max units t selll cs# low to ale low 20 ns t srheh rd# or wr# high to cs# high 60 ns t sllrl ale low to rd# low t osc ns t srlrh rd# low period t osc ns t swlwh wr# low period t osc ns t savll address valid to ale low 20 ns t sllax ale low to address invalid 20 ns t srldv rd# low to output data valid 60 ns t sdvwh input data setup to wr# high 20 ns t swhqx wr# high to data invalid 30 ns t srhdz rd# high to data float 15 ns note: 1. test conditions: f osc = 20 mhz t osc = 50 ns rise/fall time = 10 ns capacitive pin load = 100 pf 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advance information and are subject to change. a5846-01 cs ale rd p3 wr t srldv t swlwh t sllrl t selll t srheh t srlrh t savll t sllax t sdvwh t swhqx t srhdz
87c196ca/87c196cb - express 22 advance information datasheet table 11. normal master/slave operation symbol parameter min (1) max units t chch clock period 4t ns t clch clock low time/clock high time 2t?10 ns (2) t cldv clock falling to data out valid (master) 0.5t 1.5t + 20 ns t cldv1 clock falling to data out valid (slave) 0.5t 1.5t + 20 ns t dvch data in setup to clock rising edge 10 ns t chdx clock rising edge to data in invalid t + 15 ns note: 1. t = 1 state time (156.25 ns @ 20 mhz). 2. timings are guaranteed by design. table 12. handshake operation symbol parameter min (1) max units t chch clock period 4t ns t clch clock low time/clock high time 2t?10 ns (2) t cldv clock falling to data out valid (master) 0.5t 1.5t + 20 ns t cldv1 clock falling to data out valid (slave) 0.5t 1.5t + 20 ns t dvch data in setup to clock rising edge 10 ns t chdx clock rising edge to data in invalid t + 15 ns note: 1. t = 1 state time (156.25 ns @ 20 mhz). 2. this specification refers to input clocks during slave operation. during master operation, the device outputs a nominal 50% duty cycle clock.
advance information datasheet 23 87c196ca/87c196cb - express figure 14. synchronous serial port table 13. external clock drive symbol parameter min (1) max units 1/t xlxl oscillator frequency 4 20 mhz t xlxl oscillator period (t osc )50250ns t xhxx high time 0.35 x t osc 0.65 t osc ns t xlxx low time 0.35 x t osc 0.65 t osc ns t xlxh rise time 10 ns t xhxl fall time 10 ns note: 1. t = 1 state time (156.25 ns @ 20 mhz). 2. this specification refers to input clocks during slave operation. during master operation, the device outputs a nominal 50% duty cycle clock. msb d6 d5 d4 d3 d2 d1 d0 valid valid valid valid valid valid valid valid 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 sc x sd x (out) sd x (in) sc x (handshake mode) slave receiver pulls sc x low a5845-01 t chch t chcl t clch ste bit t d1dv t cxdx t cxdv t dvcx t dxcx the top scx signal assumes that the ssio is configured to sample on the leading edge with an active-high clock signal. the csx signal will be different for other configurations, however, setup and hold timings will still be the same in relation to the latching edge of scx. note:
87c196ca/87c196cb - express 24 advance information datasheet figure 15. external clock drive waveforms figure 16. input test conditions figure 17. output test conditions t xlxx a5842-01 t xhxx t xhxl t xlxl 0.3 v cc ? 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc ? 0.5 v 0.7 v cc + 0.5 v test points 2.0 v 0.8 v note: ac testing inputs are driven at 3.5 v for a logic ? 1? and 0.45 v for a logic ? 0? . timing measurements are made at 2.0 v for a logic ? 1? and 0.8 v for a logic ? 0?. 3.5 v 0.45 v a5843-01 inputs outputs v load v load ? 0.15 v v load + 0.15 v timing reference points v oh ? 0.15 v v ol + 0.15 v note: for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a5844-01
advance information datasheet 25 87c196ca/87c196cb - express 5.2.6 explanation of ac symbols each symbol is two pairs of letters prefixed by ?t? for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. 5.3 eprom specifications 5.3.1 ac eprom programming characteristics operating conditions: table 14. explanation of ac symbols conditions signals h ? high a ? address ha ? hlda# l ? low b ? bhe# l ? ale/adv# v ? valid br ? breq# q ? data out x ? no longer valid c ? clkout r ? rd# z ? floating d ? data w ? wr#/wrh#/wri# g ? buswidth x ? xtal1 h ? hold# y ? ready load capacitance = 150 pf t c = 25c 5c v ref = 5.0 v 0.5 v v cc angnd = 0 v v pp = 12.5 v 0.25 v v ss ea# = 12.5 v 0.25 v f osc = 5.0 mhz table 15. ac eprom programming characteristics (sheet 1 of 2) symbol parameter min max units t av l l address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pa l e# pu ls e widt h 5 0 t osc t plph prog# pulse width (2) ca cb 50 100 t osc t lhpl pale# high to prog# low 220 t osc t phll prog# high to next pale# low 220 t osc t phdx word dump hold time 50 t osc t phpl prog# high to next prog# low 220 t osc t lhpl pale# high to prog# low 220 t osc t pldv prog# low to word dump valid ca cb 50 100 t osc t shll reset# high to first pale# low 1100 t osc
87c196ca/87c196cb - express 26 advance information datasheet 5.3.2 eprom programming waveforms t phil prog# high to ainc# low 0 t osc t ilih ainc# pulse width 240 t osc t ilvh pver hold after ainc# low 50 t osc t ilpl ainc# low to prog# low 170 t osc t phvl prog# high to pver# valid 220 t osc notes: 1. run time programming is done with f osc = 6 mhz to 10 mhz, v cc , v pd , v ref = 5 v 0.5 v, t c = 25c 5c and v pp = 12.5 v 0.25 v. for run-time programming over a full operating range, contact factory. 2. programming specifications are not tested, but guaranteed by design. 3. this specification is for the word dump mode. for programming pulses use 300 t osc + 100 s. table 16. dc eprom programming characteristics symbol parameter min max units i pp v pp programming supply current 200 ma note: v pp must be within 1 v of v cc while v cc < 4.5 v. v pp must not have a low impedance path to ground or v ss while v cc > 4.5 v. figure 18. slave programming mode data program mode with single program pulse table 15. ac eprom programming characteristics (sheet 2 of 2) symbol parameter min max units ports 3/4 reset# address/command t avll data address/command t shll t lllh t dvpl t pldx prog# p2.2 pale# p2.1 t lhpl t plph t llax t phll pver# p2.0 t phvl valid t llvh a5838-01
advance information datasheet 27 87c196ca/87c196cb - express figure 19. slave programming mode in word dump or data verify mode with auto increment figure 20. slave programming mode timing in data program mode with repeated program pulse and auto increment ports 3/4 reset# address/command ver bits/wd dump t shll prog# p2.2 pale# p2.1 t pldv pver# p2.0 t ilpl addr addr + 2 t phdx t pldv t phdx ver bits/wd dump t a5839-01 phpl ports 3/4 reset# address/command data prog# p2.2 pale# p2.1 t phpl pver# p2.0 t phil data p1 p2 valid for p1 t ilpl valid for p2 t ilvh t ilih ainc# p2.4 a5840-01
87c196ca/87c196cb - express 28 advance information datasheet 5.4 ac characteristics - serial port - shift register mode operating conditions: t a = ?40c +85c v ss = 0.0 v v cc = 5.0 v 10% load capacitance = 100 pf 5.4.1 a/d characteristics the sample and conversion time of the a/d converter in the 8-bit or 10-bit modes is programmed by loading a byte into the ad_time special function register. this allows optimizing the a/d operation for specific applications. the ad_time register is functional for all possible values, but the accuracy of the a/d converter is only guaranteed for the times specified in the operating conditions table. the value loaded into ad_time bits 5, 6, 7 determines the sample time, samp. the value loaded into ad_time bits 0, 1, 2, 3 and 4 determines the bit conversion time, conv. these bits, as well as the equation for calculating the total conversion time, t, are shown in figure 22 . table 17. serial port timing - shift register mode symbol parameter min max units t xlxl serial port clock period 8 t osc ns t xlxh serial port clock falling edge to rising edge 4 t osc ? 50 4 t osc + 50 ns t qvxh output data setup to clock rising edge 3 t osc ns t xhqx output data hold after clock rising edge 2 t osc ? 50 ns t xhqv next output data valid after clock rising edge 2 t osc + 50 ns t dvxh input data setup to clock rising edge 2 t osc ? 200 ns t xhdx (1) input data hold after clock rising edge 0 ns t xhqz (1) last clock rising to output float 5t osc ns note: 1. parameter not tested. figure 21. waveform - serial port - shift register mode 0 a5841-01 valid valid valid valid valid valid valid valid rxd x (in) txd x 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh rxd x (out)
advance information datasheet 29 87c196ca/87c196cb - express the converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . v ref must be closed to v cc since it supplies both the resistor ladder and the analog portion of the converter and input port pins. there is also an ad_test sfr that allows for conversion on angnd and v ref as well as adjusting the zero offset. the absolute error listed is without doing any adjustments. 5.4.1.1 a/d converter specification the specifications given assume adherence to the operating conditions section of this data sheet. testing is performed with v ref = 5.12 v and 20 mhz operating frequency. after a conversion is started, the device is placed in idle mode until the conversion is completed. figure 22. ad_time 1fafh:byte 0 7654321 (samp) 4n + 1 state times n = 1 to 7 (conv) n + 1 state times n = 2 to 31 equation: t = (samp + bx (conv) + 25 t = total conversion time (states) b = number of bits conversion (8 or 10) n = programmed register value sample time bit conversion time table 18. 10-bit mode a/d operating conditions symbol parameter min max units t a ambient temperature ?40 +85 c v cc digital supply voltage 4.5 5.5 v v ref analog supply voltage 4.5 5.5 (1) v t sam sample time 2 s (2) t conv conversion time 15 18 s (2) f osc oscillator frequency 4 20 mhz notes: 1. v ref must be within+0.5 v of v cc . 2. the value of ad_time is selected to meet these specifications.
87c196ca/87c196cb - express 30 advance information datasheet table 19. 10-bit mode a/d characteristics (using above operating conditions) (1) parameter typical (2,3) min max units (4) notes resolution 1024 10 1024 10 levels bits absolute error 0 3lsbs full-scale error 0.25 0.5 lsbs zero offset error 0.25 0.5 lsbs non-linearity 1 2 3lsbs differential non-linearity > ? 0.75 + 0.75 lsbs channel-to-channel matching 0.1 0 1lsbs repeatability 0.25 0 lsbs (2) temperature coefficients: offset fullscale differential non-linearity 0.009 lsb/c (2) off isolation ? 60 db (2,4,5) feedthrough ? 60 db (2,4) v cc power supply rejection ? 60 db (2,4) input resistance 750 1.2 k ? (2) dc input leakage 10 3a voltage on analog input pin angnd ?0.5 v ref + 0.5 v (7) sampling capacitor 3 pf notes: 1. all conversions performed with processor in idle mode. 2. these values are expected for most parts at 25c but are not tested or guaranteed. 3. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 4. an ?lsb?, as used here, has a value of approximately 5 mv 5. dc to 100 khz 6. multiplexer break-before-make guaranteed. 7. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. table 20. 8-bit mode a/d operating conditions symbol parameter min max units t a ambient temperature ?40 +85 c v cc digital supply voltage 4.5 5.5 v v ref analog supply voltage 4.5 5.5 (1) v t sam sample time 2 s (2) t conv conversion time 12 15 s (2) f osc oscillator frequency 4 20 mhz notes: 1. v ref must be within+0.5 v of v cc . 2. the value of ad_time is selected to meet these specifications.
advance information datasheet 31 87c196ca/87c196cb - express table 21. 8-bit mode a/d characteristics (using above operating conditions) (1) parameter typical (2,3) min max units (4) notes resolution 256 8 1024 10 levels bits absolute error 0 1lsbs full-scale error 0.5 lsbs zero offset error 0.5 lsbs non-linearity 1lsbs differential non-linearity > ? 0.75 + 0.5 lsbs channel-to-channel matching 0 1lsbs repeatability 0.25 0 lsbs (2) temperature coefficients: offset fullscale differential non-linearity 0.003 lsb/c (2) off isolation ? 60 db (2,4,5) feedthrough ? 60 db (2,4) v cc power supply rejection ? 60 db (2,4) input resistance 750 1.2 k ? (2) dc input leakage 10 1.5 a voltage on analog input pin angnd ?0.5 v ref + 0.5 v (7) sampling capacitor 3 pf notes: 1. all conversions performed with processor in idle mode. 2. these values are expected for most parts at 25c but are not tested or guaranteed. 3. these values are not tested in production and are based on theoretical estimates and/or laboratory test. 4. an ?lsb?, as used here, has a value of approximately 5 mv 5. dc to 100 khz 6. multiplexer break-before-make guaranteed. 7. applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
87c196ca/87c196cb - express 32 advance information datasheet 5.4.2 87c196ca design considerations the 87c196ca device is a memory scalar of the 87c196kr device with integrated can 2.0. the ca is designed for strict functional and electrical compatibility to the kx family as well as integration of on-chip networking capability. the 87c196ca has fewer peripheral functions than the 196kr, due in part to the integration of the can peripheral. following are the functionality differences between the 196kr and 196ca devices. 196kr features unsupported on the 196ca: 1. external memory . removal of the buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. the programmer must define the bus mode by setting the associated bits in the ccb. 2. auto-programming mode . the 87c196ca device will only support the 16-bit zero wait state bus during auto-programming. 3. epa4 through epa7 . since the ca device is based on the kr design, these functions are in the device, however there are no associated pins. a programmer can use these as compare only channels or for other functions like software timer, start an a/d conversion, or reset timers. 4. slave port support . the slave port can not be used on the 196ca due to a function change for p5.4/slpint and p5.1/slpcs not being bonded-out. 5. port functions . some port pins have been removed. p5.1, p6.2, p6.3, p1.4 through p1.7, p2.3, p2.5, p0.0 and p0.1. the pxreg, pxssel, and pxio registers can still be updated and read. the programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. treat these bits as reserved. additionally, these port pins should be setup internally by software as follows: written to pxreg as ``1'' or ``0''. configured as push/pull, pxio as ``0''. configured as lsio. this configuration will effectively strap the pin either high or low. do not configure as open drain output `'1'', or as an input pin. this device is cmos. 6. epa timer reset/write conflict . if the user writes to the epa timer at the same time that the timer is reset, it is indeterminate which will take precedence. users should not write to a timer if using epa signals to reset it. 7. valid time matches . the timer must increase/decrease to the compare value for a match to occur. a match does not occur if the timer is loaded with a value equal to an epa compare value. matches also do not occur if a timer is reset and 0 is the epa compare value. 8. write cycle during reset . if reset occurs during a write cycle, the contents of the external memory device may be corrupted. 9. indirect shift instruction . the upper 3 bits of the byte register holding the shift count are not masked completely. if the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. this should have resulted in no shift taking place. 10. p2.7 (clkout) . p2.7 (clkout) does not operate in open drain mode. analog channels 0 and 1 inst pin functionality slpint and slpcs pin support hld/hlda functionality external clocking/direction of timer1 quadrature clocking timer 1 dynamic buswidth epa capture channels 47
advance information datasheet 33 87c196ca/87c196cb - express 5.4.3 87c196ca design considerations 1. port0 on the 87c196ca the analog inputs for p0.0 and p0.1 have been multiplexed and tied to v ref . therefore, initiating an analog conversion on ach0 or ach1 results in a value equal to full scale (3ffh). on the ca, the digital inputs for these two channels are tied to ground, therefore, reading p0.0 or p0.1 results in a digital ?0?. 2. port1 on the 87c196ca, p1.4, p1.5, p1.6 and p1.7 have been removed from the device and is not available to the programmer. corresponding bits in the port registers have been ?hard-wired? to provide the following results when read: 3. port2 on the 87c196ca, p2.3 and p2.5 have been removed from the device and are not available to the programmer. corresponding bits in the port registers have been ?hard-wired? to provide the following results when read. 4. port5 on the 87c196ca, p5.1 and p5.7 have been removed from the device and are not available to the programmer. corresponding bits in the port registers have been ?hard-wired? to provide the following results when read: 5. port6 register bits when read p1_pin.x (x = 4,5,6,7) 1 p1_reg.x (x = 4,5,6,7) 1 p1_dir.x (x = 4,5,6,7) 1 p1_mode.x (x = 4,5,6,7) 0 note: writing to these bits has no effect. register bits when read p2_pin.x (x = 3,5) 1 p2_reg.x (x = 3,5) 1 p2_dir.x (x = 3,5) 1 p2_mode.x (x = 3,5) 0 note: writing to these bits has no effect. register bits when read p5_pin.x (x = 1,7) 1 p5_reg.x (x = 1,7) 1 p5_dir.x (x = 1,7) 1 p5_mode.x (x = 1) 0 p5_mode.x (x = 7) 1 note: writing to these bits has no effect.
8 7 c 196 ca / 8 7 c 196 c b - exp r e s s 3 4 advanc e i n f o r m a t i o n da t a s h e e t o n t h e 87c 1 96ca , p 6 . 2 a nd p 6 . 3 h a v e b e e n r e m ov e d fr o m th e d e v i c e a nd a r e not a v a i l a bl e t o t h e p r ogr a m m e r . co r r e s po n ding b i t s i n th e p ort r e g i s t e r s h a v e b ee n h a r d-wir e d to p r ovi d e th e f o l l owing r e s u lt s whe n r e a d : 6 . 0 d a t a s h e e t r e visi o n h ist o r y for r e v -0 0 2 o f t hi s d a t a s h e e t, t h e f r e qu e n c y a nd p e riod s p e c i f i c a t i on s for c l o c k i n put h a v e b e e n up d a t e d fro m 1 6 mh z c l o c k i nput , 62 . 5 n s c l o c k p e r i od to 20 mh z c l o c k i nput a n d 5 0 n s p e r i od . r e g i s t er b i t s w h e n r e a d p 6 _p i n . x ( x = 2 , 3 ) 1 p 6 _ r e g . x ( x = 2 , 3 ) 1 p 6 _ d ir . x ( x = 2 , 3 ) 1 p 6 _m od e . x ( x = 2 , 3 ) 0 n o t e : w r i ti ng t o t h e s e b it s h a s n o e f f ec t . 1 . to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". for r e v -0 0 3 o f t hi s d a t a s h e e t, t h e following changes were made:

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